- #Simple fpga simulation waveform verification#
- #Simple fpga simulation waveform software#
- #Simple fpga simulation waveform simulator#
In less time than it takes to upload the simulation kernel and test vectors to a simulation farm, you can be happily probing your actual FPGA hardware implementation with virtual instrumentation, running the design at speeds that would make the simulation savants green with envy. In FPGA design, however, the heavy lifting is done in hardware.
#Simple fpga simulation waveform verification#
The number of events that can be evaluated on a code-crunching farm of five hundred air-conditioned Linux boxes during a 48-hour run is the most meaningful metric to the hard-core ASIC verification crowd.
#Simple fpga simulation waveform simulator#
As a designer you should be aware of what you need and have patience with the product vendors, who are understandably confused.įor ASIC design, the key attributes of an HDL simulator are (in order) speed, speed, speed, and capacity. The requirements, however, are really quite different. When you’re used to selling your product to ASIC designers as a verification tool, it’s difficult to turn around and sell the same product to an FPGA audience as a development and debug aid.
#Simple fpga simulation waveform software#
Most modern FPGAs are developed primarily in VHDL and Verilog, and the HDL simulator is as important to the development of that code as a debugger is to a software developer.įor multi-purpose marketers at EDA companies, it’s hard to break the habit. HDL simulation is an integral part of FPGA design - just not in the role of verification. Thanks to ASIC design, the concepts of HDL simulation and “verification” are so tightly connected that few are able to entertain the idea that HDL simulation could be used for any other purpose. The keystone of all modern ASIC verification tools is the venerable HDL simulator. Spending tens of thousands for software tools that are more than an order of magnitude slower and don’t model the hardware as accurately just doesn’t make sense. They do, of course, but given the state of modern development boards, reprogrammable architectures, and on-chip hardware/software debugging with high-bandwidth data transfer and robust user interfaces, the only sensible way to verify FPGA designs is using an HIL (Hardware-In-the-Loop) approach. This is not to say that production FPGA designs don’t need to be verified before they’re shipped. There simply is no way to justify significant investment in software verification tools for the design of FPGAs. People use FPGAs every day as a platform for prototyping ASIC designs in hardware for accelerated verification. FPGAs, in fact, are one of the leading verification technologies for ASIC design. For FPGA design, there is no such penalty. In addition to those penalties, each re-spin to correct an error carries immeasurable impact in missed market opportunity. For ASIC design, the second term is measured in hundreds of thousands of dollars and weeks of schedule time. The second term, cost of correction, however, is where the problem occurs. The more we invest in verification, the smaller the first term (likelihood of error) gets. The sensible investment in verification tools, then, is proportional to the likelihood of an error making it through to hardware multiplied by the cost of correcting that error.
It represents an investment of time and resources to reduce overall risk. It is the final “let’s be sure” step that catches any last minute problems that crept into your code. “Verification” is what you do to make sure that your design is correct before you commit it to hardware. Without so much as a pause to ponder, they mimic the mantras of the ASIC world: “Well, if your FPGA designs are reaching five million gates, you’re going to need some sophisticated verification tools.” It stands to reason, then, that when FPGA designs began to reach the same complexity as ASIC designs, EDA companies and ASIC designers would have a Pavlovian response, driving them immediately to the question of “verification”. Capitalizing on the risk inherent in the ASIC design flow, they produce premium-priced solutions that seek to siphon off the inevitable human failures that find their way into complex engineering projects. “Verification” is what EDA companies have learned to trust as their bread-and-butter. “Verification” is what you do to protect your job so you’re not blamed with an expensive and time-consuming re-spin of an ASIC design. “Verification” is the long pole in the tent, the most time-consuming phase of the design cycle. In the ASIC design world, where risk avoidance is everything, “verification” is a sacred term. When someone uses the words “verification” and “FPGA” in the same sentence, I’m always suspicious.
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